Output Directory Changes

.gitignore

@@ -0,0 +1 @@
+**/[Oo]ut_*

fpga/run.tcl

@@ -8,34 +8,37 @@ set fp [open "tmp.txt" r]
 set content [read $fp]
 close $fp
 set lines [split $content \n]
-set file_name [lindex $lines 0]
-set part_name [lindex $lines 1]
-set cons_name [lindex $lines 2]
+set file_name  [lindex $lines 0]
+set part_name  [lindex $lines 1]
+set cons_name  [lindex $lines 2]
 set shell_path [lindex $lines 3]
+set board	   [lindex $lines 4]
 
 #
-# STEP#1: define output directory area.
+# STEP#1: define output and input directory area.
 #
-set outputDir ./out_${file_name}_${part_name}/FPGA_${file_name}
+# set outputDir ./out_${file_name}_${part_name}/FPGA_${file_name}
+set outputDir ./../out/${board}/${file_name}/Output
+set inputDir ./../out/${board}/${file_name}/Dependencies
 file mkdir $outputDir
 
 #
 # STEP#2: setup design sources and constraints
 #
-read_verilog ./out_${file_name}_${part_name}/${file_name}.v
-read_verilog ./out_${file_name}_${part_name}/includes/proj_verilog/clk_gate.v
+read_verilog $inputDir/${file_name}.v
+read_verilog $inputDir/includes/proj_verilog/clk_gate.v
 #read_verilog ${shell_path}/../../includes/clock_divider.v
 #set_property -include_dirs {./out_${file_name}_${part_name}/includes/* ./out_${file_name}_${part_name}/includes/proj_verilog/* ./out_${file_name}_${part_name}/includes/proj_default/*} [current_fileset]
 read_xdc $cons_name
-read_xdc ./out_${file_name}_${part_name}/clock_constraints.xdc
+read_xdc $inputDir/clock_constraints.xdc
 
 #
 # STEP#3: run synthesis, report utilization and timing estimates, write checkpoint design
 #
 set multi_include_dirs " \
-./out_${file_name}_${part_name}/includes \
-./out_${file_name}_${part_name}/includes/proj_verilog \
-./out_${file_name}_${part_name}/includes/proj_default \
+$inputDir/includes \
+$inputDir/includes/proj_verilog \
+$inputDir/includes/proj_default \
 "
 synth_design -top top -part $part_name -retiming -include_dirs $multi_include_dirs
 file mkdir $outputDir/syn/reports
@@ -122,7 +125,7 @@ write_bitstream -force $outputDir/$file_name.bit
 #
 # STEP#7: connect to your board
 #
-open_hw
+open_hw_manager
 connect_hw_server
 open_hw_target
 #current_hw_device [lindex [get_hw_devices] 0]

out/basys3/led_counter/Dependencies/clock_constraints.xdc

@@ -0,0 +1,3 @@
+create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
+set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports reset]
+set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports reset]

out/basys3/led_counter/Dependencies/includes/proj_default/clk_gate.sv

@@ -0,0 +1,38 @@
+/*
+Copyright (c) 2014, Steven F. Hoover
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * The name of Steven F. Hoover
+      may not be used to endorse or promote products derived from this software
+      without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+// Clock gate module used by SandPiper default project.
+
+// Note: No X injection for X on free_clk.)
+module clk_gate (output logic gated_clk, input logic free_clk, func_en, pwr_en, gating_override);
+   logic clk_en;
+   logic latched_clk_en  /*verilator clock_enable*/;
+   always_comb clk_en = func_en & (pwr_en | gating_override);
+   always_latch if (~free_clk) latched_clk_en <= clk_en;
+             // latched_clk_en <= (~free_clk) ? clk_en : latched_clk_en;
+   always_comb gated_clk = latched_clk_en & free_clk;
+endmodule

out/basys3/led_counter/Dependencies/includes/proj_default/sp_default.vh

@@ -0,0 +1,8 @@
+`ifndef SP_DEFAULT
+`define SP_DEFAULT
+
+// File included by SandPiper-generated code for the default project configuration.
+`include "sandpiper.vh"
+
+
+`endif  // SP_DEFAULT

out/basys3/led_counter/Dependencies/includes/proj_verilog/clk_gate.v

@@ -0,0 +1,39 @@
+/*
+Copyright (c) 2015, Steven F. Hoover
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * The name of Steven F. Hoover
+      may not be used to endorse or promote products derived from this software
+      without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+`include "sp_verilog.vh"
+
+
+// Clock gate module used by SandPiper default project.
+
+module clk_gate (output gated_clk, input free_clk, func_en, pwr_en, gating_override);
+   wire clk_en;
+   reg latched_clk_en  /*verilator clock_enable*/;
+   assign clk_en = func_en & (pwr_en | gating_override);
+   `TLV_BLATCH(latched_clk_en, clk_en, free_clk)
+   assign gated_clk = latched_clk_en & free_clk;
+endmodule

out/basys3/led_counter/Dependencies/includes/proj_verilog/sp_verilog.vh

@@ -0,0 +1,65 @@
+`ifndef SP_DEFAULT
+`define SP_DEFAULT
+/*
+Copyright (c) 2015, Steven F. Hoover
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * The name of Steven F. Hoover
+      may not be used to endorse or promote products derived from this software
+      without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+
+// File included by SandPiper-generated code for the default project configuration.
+`include "sandpiper.vh"
+
+
+// Latch macros.  Inject 'x in simulation for clk === 'x.
+
+// A-phase latch.
+`ifdef SP_PHYS
+`define TLV_LATCH(in, out, clk) \
+always @ (in, clk) begin        \
+  if (clk === 1'b1)             \
+    out <= in;                  \
+  else if (clk === 1'bx)        \
+    out <= 'x;                  \
+end
+`else
+`define TLV_LATCH(in, out, clk) always @ (in, clk) if (clk == 1'b1) out <= in;
+`endif  // SP_PHYS
+
+// B-phase latch.
+`ifdef SP_PHYS
+`define TLV_BLATCH(out, in, clk) \
+always @ (in, clk) begin         \
+  if (!clk === 1'b1)             \
+    out <= in;                   \
+  else if (!clk === 1'bx)        \
+    out <= 'x;                   \
+end
+`else
+`define TLV_BLATCH(out, in, clk) always @ (in, clk) if (!clk == 1'b1) out <= in;
+`endif  // SP_PHYS
+
+
+
+`endif  // SP_DEFAULT

out/basys3/led_counter/Dependencies/includes/pseudo_rand.tlv

@@ -0,0 +1,69 @@
+\m4_TLV_version 1b: tl-x.org
+\SV
+/*
+Copyright (c) 2014, Steven F. Hoover
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+    * Redistributions of source code must retain the above copyright notice,
+      this list of conditions and the following disclaimer.
+    * Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+    * The name of Steven F. Hoover
+      may not be used to endorse or promote products derived from this software
+      without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+module pseudo_rand
+  #(parameter WIDTH=257)  // Random vector width, to a max of 257.
+  (input  logic clk,
+   input  logic reset,
+   output logic [WIDTH-1:0] rand_vect
+  );
+
+// Currently, this implements a Galois LFSR.
+// TODO: It should be XORed with something else so it doesn't just shift.
+//       Using polynomials with maximal number of taps would have less regular shifting behavior.
+
+// Bits are numbered in the reverse of the traditional order.  This puts the taps in the lower bit positions.
+
+// Choose optimal parameters for given WIDTH.
+localparam LFSR_WIDTH =
+  (WIDTH <= 64)   ? 64   :
+  (WIDTH <= 128)  ? 128  :
+  (WIDTH <= 257)  ? 257  : 0;   // 257 enables a large non-power of two for replication on an irregular boundary.
+// Polynomial source: http://www.eej.ulst.ac.uk/~ian/modules/EEE515/files/old_files/lfsr/lfsr_table.pdf
+localparam [LFSR_WIDTH-1:0] LFSR_POLY = {{(LFSR_WIDTH-8){1'b0}},
+  (LFSR_WIDTH == 64)   ? 8'b00011011 :
+  (LFSR_WIDTH == 128)  ? 8'b10000111 :
+  (LFSR_WIDTH == 257)  ? 8'b11000101 : 8'b0};
+
+bit [256:0] SEED = 257'h0_7163e168_713d5431_6684e132_5cd84848_f3048b46_76874654_0c45f864_04e4684a;
+
+
+
+\TLV
+   |default
+      @0
+         $reset = reset;
+      @1
+         $lfsr[LFSR_WIDTH-1:0] = $reset ? *SEED : {$lfsr#+1[LFSR_WIDTH-2:0], 1'b0} ^ ({LFSR_WIDTH{$lfsr#+1[LFSR_WIDTH-1]}} & *LFSR_POLY);
+      @2
+         *rand_vect = $lfsr[WIDTH-1:0];
+
+\SV
+
+endmodule

out/basys3/led_counter/Dependencies/includes/rw_lib.vh

@@ -0,0 +1 @@
+`define RW_ZX(in, width) {{width-$width(in){1'b0}}, in}

out/basys3/led_counter/Dependencies/includes/sandhost/README.txt

@@ -0,0 +1 @@
+Veriog include files that are available only within Makerchip.

out/basys3/led_counter/Dependencies/includes/sandhost/sqrt32.v

@@ -0,0 +1,13 @@
+// A non-synthesizable Verilog-2005 sqrt function for tutorials.
+`ifndef RW_NON_SYNTH_SQRT
+`define RW_NON_SYNTH_SQRT
+
+function [31:0] sqrt;
+   input [31:0] a;
+
+   /* verilator lint_off REALCVT */
+   sqrt = $sqrt(a);
+   /* verilator lint_on REALCVT */
+endfunction
+
+`endif

out/basys3/led_counter/Dependencies/includes/sandhost/tb.sv

@@ -0,0 +1,76 @@
+// Provides clk and reset to design.tlv.
+// Instantiates design as design(.*) so additional inputs and outputs can be added.
+// Ends simulation on max cycles argument below, or assertion of success signal.
+// Additional testbench functionality can be added here, or within design using TLV.
+// See: "top_module_tlv.m4" for definition.
+
+// -------------------------------------------------------------------
+// Expanded from instantiation: m4_top_module_inst(m4_name, m4_max_cycles)
+//
+
+module tb();
+
+logic clk, reset;      // Generated in this module for DUT.
+logic passed, failed;  // Returned from DUT to this module.  Passed must assert before
+                       //   max cycles, without failed having asserted.  Failed can be undriven.
+logic [15:0] cyc_cnt;
+
+
+// Instantiate main module.
+top top(.*);
+
+
+// Clock
+initial begin
+   clk = 1'b1;
+   forever #5 clk = ~clk;
+end
+
+
+// Run
+initial begin
+
+   //`ifdef DUMP_ON
+      $dumpfile("top.vcd");
+      $dumpvars(0, clk, reset, passed, failed, cyc_cnt, top.DEBUG_SIGS);
+      $dumpon;
+   //`endif
+
+   reset = 1'b1;
+   #55;
+   reset = 1'b0;
+
+   // Run
+
+   cyc_cnt = '0;
+   for (int cyc = 0; cyc < 100; cyc++) begin
+      // Failed
+      if (failed === 1'b1) begin
+         FAILED: assert(1'b1) begin
+            $display("Failed!!!  Error condition asserted.");
+            $finish;
+         end
+      end
+
+      // Success
+      if (passed) begin
+         SUCCESS: assert(1'b1) begin
+            $display("Success!!!");
+            $finish;
+         end
+      end
+
+      #10;
+
+      cyc_cnt++;
+   end
+
+   // Fail
+   DIE: assert (1'b1) begin
+      $error("Failed!!!  Test did not complete within m4_max_cycles time.");
+      $finish;
+   end
+
+end
+
+endmodule  // life_tb